Title :
Digital background calibration for timing mismatch in time-interleaved ADCs
Author :
Chen, H.-H. ; Lee, J. ; Chen, J.-T.
Author_Institution :
Inst. of Commun. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
A digital background calibration for minimising timing-error effects in time-interleaved analogue-to-digital converter (TIADC) is presented. A technique for correcting sampling time error in a four-channel TIADC system is described. Simulation results show that the proposed calibration technique can significantly improve the signal-to-noise-and-distortion ratio (SNDR) performance for the 12-bit TIADC system.
Keywords :
analogue-digital conversion; calibration; error correction; 12 bit; 12-bit TIADC system; ADC; digital background calibration; four-channel system; sampling time error correction; signal-to-noise-distortion ratio; time-interleaved analogue-to-digital converter; timing mismatch; timing-error effects minimisation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20063387
