• DocumentCode
    805211
  • Title

    Digital background calibration for timing mismatch in time-interleaved ADCs

  • Author

    Chen, H.-H. ; Lee, J. ; Chen, J.-T.

  • Author_Institution
    Inst. of Commun. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • Volume
    42
  • Issue
    2
  • fYear
    2006
  • Firstpage
    74
  • Lastpage
    75
  • Abstract
    A digital background calibration for minimising timing-error effects in time-interleaved analogue-to-digital converter (TIADC) is presented. A technique for correcting sampling time error in a four-channel TIADC system is described. Simulation results show that the proposed calibration technique can significantly improve the signal-to-noise-and-distortion ratio (SNDR) performance for the 12-bit TIADC system.
  • Keywords
    analogue-digital conversion; calibration; error correction; 12 bit; 12-bit TIADC system; ADC; digital background calibration; four-channel system; sampling time error correction; signal-to-noise-distortion ratio; time-interleaved analogue-to-digital converter; timing mismatch; timing-error effects minimisation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20063387
  • Filename
    1582060
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=805211