Electron and hole mobility enhancement in strained SOI by wafer bonding

Author

Huang, Lijuan ; Chu, Jack O. ; Goma, S.A. ; D´Emic, C.P. ; Koester, Steven J. ; Canaperi, Donald F. ; Mooney, Patricia M. ; Cordes, S.A. ; Speidell, James L. ; Anderson, R.M. ; Wong, H. S Philip

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

49

Issue

9

fYear

2002

fDate

9/1/2002 12:00:00 AM

Firstpage

1566

Lastpage

1571

Abstract

N- and p-MOSFETs have been fabricated in strained Si-on-SiGe-on-insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 50% for electrons (with 15% Ge) and 15-20% for holes (with 20-25% Ge) has been demonstrated in SSOI MOSFETs. These mobility enhancements are commensurate with those reported for FETs fabricated on strained silicon on bulk SiGe substrates

Keywords

CMOS integrated circuits; Ge-Si alloys; MOSFET; electron mobility; elemental semiconductors; hole mobility; semiconductor materials; silicon; silicon-on-insulator; substrates; wafer bonding; CMOS circuits; H; H-induced layer transfer techniques; Si-SiGe; SiGe; electron mobility enhancement; fabrication; high Ge content; hole mobility enhancement; n-MOSFETs; p-MOSFETs; strained SOI; strained Si-on-SiGe-on-insulator; substrates; wafer bonding; Annealing; Charge carrier processes; Electron mobility; Fabrication; Germanium silicon alloys; MOSFET circuits; Silicon germanium; Silicon on insulator technology; Temperature; Wafer bonding;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2002.802675

Filename

1027838