Setting the trap for hot carriers [MOS VLSI]

The device degradation under ac and dc stress have been discussed and a relationship between the two has been established,. We have shown that the commonly used lifetime criteria of 10% linear current degradation for 10 years for a transistor under dc stress is overly conservative for representing the circuit operating lifetime. Using experimental and simulated data for inverter chains, we proposed that a meaningful equivalent lifetime based on 10% I/sub dl/ degradation under dc stress is 1 year lifetime (for a 10 year circuit lifetime based on 54b degradation in ring oscillator frequency). We also compared this criteria to actual circuit degradation for microprocessors and a DRAM. For DSP microprocessors with 0.8 μm LDD transistors, the projected lifetime was more than 200 years at 5.5 V, with a corresponding 10% I/sub dr/ lifetime of 20 years. For 1 Mb DRAMs with 1 pm LDD transistors, the 5% speed degradation lifetime at 5.5 V was more than 100 years, whereas the individual transistors had 10% I/sub dl/ lifetime of 4 years. These circuit results support the 10% I/sub dl/ transistor lifetime. We believe these criterion should be very safe and reasonable for digital IC chips currently in the field, as well as those in future design and development.