Effects of neglecting carrier tunneling on electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs

We investigate the validity of the assumption of neglecting carrier tunneling effects on the self-consistent electrostatic potential in calculating the direct tunneling gate current in deep submicron MOSFETs. A comparison between simulated and experimental results shows that for accurate modeling of direct tunneling current, tunneling effects on potential profile need to be considered. The relative error in gate current due to neglecting carrier tunneling is higher at higher gate voltages and increases with decreasing oxide thickness. We also study the direct tunneling gate current in MOSFETs with high-K gate dielectrics