DocumentCode
805810
Title
Early, accurate dependability analysis of CAN-based networked systems
Author
Acle, Julio Pérez ; Reorda, Matteo Sonza ; Violante, Massimo
Author_Institution
Inst. de Ingenieria Electrica, Univ. de la Republica, Montevideo, Uruguay
Volume
23
Issue
1
fYear
2006
Firstpage
38
Lastpage
45
Abstract
Many safety-critical applications today rely on computer-based systems in which several computing nodes communicate through a network backbone. As the complexity of the systems under analysis grows, designers must devise fault-injection models that strike a balance between two conflicting requirements: On the one hand, models should be as close as possible to a system´s physical implementation to reflect precisely the effects of real faults. On the other hand, abstract, easily manageable models minimize the time required for the fault-injection experiments, letting designers analyze sets of faults wide enough to provide statistically meaningful information. In addressing this issue, we have devised a fault-injection environment to study the effects of soft errors in CAN networks. Our cosimulation environment consists of two modules. The first, a traffic generator module implemented in software, emulates the applications running in each node of the network. The second, a network backbone module implemented in hardware, simulates the activities involved in information exchange between network nodes, in compliance with the CAN protocol specification. To allow evaluation of complex workloads as well as large fault lists, we use an FPGA board to emulate the network backbone module. This enables cycle-accurate simulations of the entire network´s behavior with very low speed penalties.
Keywords
controller area networks; fault diagnosis; protocols; CAN protocol specification; CAN-based networked systems; FPGA; cosimulation environment; dependability analysis; fault-injection environment; network backbone module emulation; traffic generator module; Application software; Computer errors; Computer networks; Field programmable gate arrays; Hardware; Information analysis; Protocols; Spine; Telecommunication traffic; Traffic control; fault injection; fault tolerance; network architecture and design; real-time and embedded systems;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2006.10
Filename
1583537
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