Title :
A macro analysis of soft errors in static RAMs
Author :
Nakase, Yasunobu ; Anami, Kenji ; Shiomi, Tohru ; Ohba, Atsushi ; Kayano, Shinpei
Author_Institution :
Mitsubishi Electr. Corp., Itami, Japan
fDate :
4/1/1988 12:00:00 AM
Abstract :
In the soft error phenomenon in static RAMs (SRAMs), the mechanism of data upset is more complicated than in dynamic RAMs (DRAMs) because the storage nodes in the memory cells are connected to the power supply via load element. Therefore the critical charge has been evaluated only by computer simulation. The charge which is supplied via load element is estimated analytically, assuming α-particle-induced current being constant. The charge which is fed through the load element contributes to the increase of the critical charge in a 1-kbit emitter-coupled logic (ECL) RAM with a 10-kΩ resistor load. In ECL RAMs or MOS SRAMs with a larger resistor, the contribution of the charge which is fed through the load element is hardly expected, and the critical change in such RAMs is evaluated by the stored charge like DRAMs
Keywords :
bipolar integrated circuits; emitter-coupled logic; field effect integrated circuits; integrated memory circuits; random-access storage; α-particle-induced current; 1 kbit; 10 kohm; ECL RAMs; MOS SRAMs; SRAMs; alpha particles; critical charge; load resistance; macro analysis; mechanism of data upset; soft error phenomenon; soft errors; static RAMs; storage nodes; Circuit noise; Computer errors; Computer simulation; DRAM chips; Equivalent circuits; Error analysis; Logic; Parasitic capacitance; Power supplies; Random access memory; Read-write memory; Resistors;
Journal_Title :
Solid-State Circuits, IEEE Journal of
