Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler

Author

Yu, Xiao Peng ; Do, Manh Anh ; Lim, Wei Meng ; Yeo, Kiat Seng ; Ma, Jian-Guo

Author_Institution

VLSI Design, Zhejiang Univ., Hangzhou

Volume

54

Issue

11

fYear

2006

Firstpage

3828

Lastpage

3835

Abstract

The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this divide-by-2/3 unit using a 0.18-mum CMOS process is capable of operating up to 4 GHz with a low-power consumption. The prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications

Keywords

CMOS digital integrated circuits; frequency dividers; high-speed integrated circuits; low-power electronics; prescalers; wireless LAN; 0.18 micron; 4 GHz; CMOS integrated circuit; frequency divider; high-speed digital circuit; short-circuit power; switching power; true single-phase clock; wireless local area network; CMOS technology; Clocks; Design optimization; Digital circuits; Energy consumption; Flip-flops; Frequency conversion; Frequency synthesizers; Integrated circuit synthesis; Propagation delay; CMOS integrated circuit; D flip-flop (DFF); frequency divider; frequency synthesizer; high-speed digital circuit; phase-locked loops (PLLs); true single-phase clock (TSPC);

fLanguage

English

Journal_Title

Microwave Theory and Techniques, IEEE Transactions on

Publisher

ieee

ISSN

0018-9480

Type

jour

DOI

10.1109/TMTT.2006.884629

Filename

1717749