Multiple serial and parallel concatenated single parity-check codes

Single parity-check (SPC) codes are applied in both parallel and serial concatenated structures to produce high-performance coding schemes. The number of concatenations or stages, M, is increased to improve system performance at moderate-to-low bit-error rates without changing the overall code parameters (namely, code rate and code block length). Analytical bounds are presented to estimate the performance at high signal-to-noise ratios. The SPC concatenated codes are considered with binary phase-shift keying and with 16-quadrature amplitude modulation bit-interleaved coded modulation on the additive white Gaussian noise channel and the independent Rayleigh fading channel. Simulations show that the four-stage serial or parallel concatenated SPC codes can, respectively, outperform or perform as well as 16-state turbo codes. Furthermore, decoding complexity is approximately 9-10 times less complex than that of 16-state turbo codes. The convergence behavior of both serial and parallel concatenated SPC codes is also discussed.