Hard-wired multipliers with encoded partial products

Author

Vassiliadis, Stamatis ; Schwarz, Eric M. ; Sung, Baik M.

Author_Institution

IBM, Endicott, NY, USA

Volume

40

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

1181

Lastpage

1197

Abstract

A multibit overlapped scanning multiplication algorithm for sign-magnitude and two´s complement hard-wired multipliers is presented. The theorems necessary to construct the multiplication matrix for sign-magnitude representations are emphasized. Consequently, the algorithm for sign-magnitude multiplication and its variation to include two´s complement numbers are presented. The proposed algorithm is compared to previous algorithms that generate a sign extended partial product matrix, with an implementation and with a study of the number of elements in the partial product matrix. The proposed algorithm is shown to yield significant savings over well known algorithms for the generation and the reduction of the partial product matrix of a multiplier designed with multibit overlapped scanning

Keywords

digital arithmetic; encoding; multiplying circuits; encoded partial products; hardwired multipliers; multibit overlapped scanning multiplication algorithm; sign-magnitude; two´s complement; Algorithm design and analysis; Assembly systems; Counting circuits; Cryptography; Decoding; Digital arithmetic; Hardware; Iterative algorithms; Iterative methods; Performance gain;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.102823

Filename

102823