Title :
Impact of H2 High-Pressure Annealing Onto InGaAs Quantum-Well Metal–Oxide–Semiconductor Field-Effect Transistors With Al2O3/HfO2 Gate-Stack
Author :
Tae-Woo Kim ; Hyuk-Min Kwon ; Seung Heon Shin ; Chan-Soo Shin ; Won-Kyu Park ; Chiu, Eddie ; Rivera, Manny ; Lew, Jae Ik ; Veksler, Dmitry ; Orzali, Tommaso ; Dae-Hyun Kim
Author_Institution :
SEMATECH, Inc., Albany, NY, USA
Abstract :
We report on the impact of H2 high-pressure annealing (HPA) onto In0.7Ga0.3As MOSCAPs and quantum-well (QW) MOSFETs with Al2O3/HfO2 gate-stack. After HPA with process condition of 300°C, H2 ambient and pressure of 20 atm, we observed notable improvements of the capacitance-voltage (CV) characteristics in InGaAs MOSCAPs with Al2O3/HfO2 gate-stack, such as reduction of equivalent-oxide-thickness and less frequency dispersion in the accumulation region. There was 20% improvement of the interfacial trap density (Dit). Then, we incorporated the HPA process into the fabrication of sub-100-nm In0.7Ga0.3As QW MOSFETs, to investigate the impact of HPA process. After HPA process, the device with Lg = 50 nm exhibits improved subthreshold-swing (SS) = 105 mV/decade, in comparison with SS = 130 mV/decade for the reference device without HPA process. Finally, we carried out reliability assessment under a constant-voltage-stress (CVS), and it turns out that the HPA process was effective in mitigating a shift of threshold voltage (ΔVT) during the CVS. These are attributed to the effective passivation of oxide traps in the high-k dielectric layer and interfacial traps, after HPA process in the H2 ambient.
Keywords :
III-V semiconductors; MOSFET; aluminium compounds; annealing; gallium arsenide; hafnium compounds; high-k dielectric thin films; hydrogen; indium compounds; semiconductor device reliability; semiconductor quantum wells; Al2O3-HfO2; CVS; H2 high-pressure annealing; H2; HPA; In0.7Ga0.3As; MOSCAP; QW MOSFET; capacitance-voltage characteristics; constant-voltage-stress; equivalent-oxide-thickness; frequency dispersion; high-k dielectric layer; interfacial trap density; interfacial traps; oxide traps; passivation; pressure 20 atm; quantum-well MOSFET; reliability assessment; size 100 nm; size 50 nm; temperature 300 C; threshold voltage; Aluminum oxide; Annealing; Hafnium compounds; Indium gallium arsenide; Logic gates; MOSFET; Passivation; In0.53Ga0.47As MOSFET; InGaAs MOSFET; atomic layer deposition (ALD); high-pressure annealing; interfacial trap density (Dit); subthreshold-swing (SS);
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2015.2438433