Title :
Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFET
Author :
Kumar, Jagadesh M. ; Verma, Vikram
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India
fDate :
9/1/2002 12:00:00 AM
Abstract :
For the first time, we report the combined application of a SiGe source and a delta-doped p+ region in a PD SOI MOSFET to minimize the impact of floating body effect on both the drain breakdown voltage and the single transistor latch. Our results demonstrate that the proposed SOI structure exhibits as large as 200% improvement in the breakdown voltage and is completely immune to single transistor latch when compared to the conventional SOI MOSFET thus improving the reliability of these structures in VLSI applications
Keywords :
Ge-Si alloys; MOSFET; electric breakdown; semiconductor device reliability; silicon-on-insulator; CMOS reliability; VLSI applications; bipolar induced drain breakdown elimination; breakdown voltage improvement; delta-doped p+ region; drain breakdown voltage; floating body effect impact minimisation; reliability improvement; single transistor latch; submicron PD SOI MOSFET; CMOS integrated circuits; Electric breakdown; Germanium silicon alloys; Immune system; Integrated circuit reliability; Latches; MOSFET circuits; Silicon germanium; Silicon on insulator technology; Very large scale integration;
Journal_Title :
Reliability, IEEE Transactions on
DOI :
10.1109/TR.2002.801851
