DocumentCode
807799
Title
An 8-b 650-MHz folding ADC
Author
Van Valburg, Johan ; Van De Plassche, Rudy J.
Author_Institution
Philips Res. Lab., Endhoven, Netherlands
Volume
27
Issue
12
fYear
1992
fDate
12/1/1992 12:00:00 AM
Firstpage
1662
Lastpage
1666
Abstract
An 8-b 650-MHz folding analog-to-digital converter (ADC) with analog error correction in the comparators is presented. With an input frequency of 150 MHz, 7.8 effective bits are obtained. The ADC is implemented in a 1-μm 13-GHz triple-level interconnect bipolar process, requiring 850 mW from a single -4.5 V supply. The die size is 4.2 mm2
Keywords
analogue-digital conversion; bipolar integrated circuits; error correction; -4.5 V; 1 micron; 650 MHz; 8 bit resolution; 850 mW; A/D convertor; analog error correction; comparators; folding ADC; monolithic IC; triple-level interconnect bipolar process; Digital-analog conversion; Energy consumption; Error correction; Frequency conversion; Helium; Power amplifiers; Quantization; Sampling methods; Signal sampling; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.173091
Filename
173091
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