• DocumentCode
    807928
  • Title

    Conversion of redundant binary into two´s complement representations

  • Author

    Herrfeld, A. ; Hentschke, S.

  • Author_Institution
    Inst. fur Periphere Mikroelektronik, Kassel Univ., Germany
  • Volume
    31
  • Issue
    14
  • fYear
    1995
  • fDate
    7/6/1995 12:00:00 AM
  • Firstpage
    1132
  • Lastpage
    1133
  • Abstract
    A static CMOS circuit that converts a redundant binary representation into a two´s complement representation is presented. The structure and time delay of the resulting logic are identical to a standard carry look-ahead logic for adders. The resulting layout is very regular, has no diffusion gaps and can be expanded to any desired look-ahead length. The circuit can be used for both multiplication and division
  • Keywords
    CMOS logic circuits; carry logic; redundant number systems; carry look-ahead logic; digital arithmetic; division; multiplication; redundant binary representation; static CMOS circuit; time delay; two´s complement representation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19950791
  • Filename
    398576
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=807928