Title :
Design of most-significant-bit-first serial multiplier
Author :
Lu, Shih-Lien ; Kenney, J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
fDate :
7/6/1995 12:00:00 AM
Abstract :
The design of a two´s complement most-significant-bit-first add and shift serial multiplier is presented. In this multiplier, one of the multiplicands is represented in full length, whereas the second multiplicand is presented in a bit-serial fashion with the most significant bit (MSB) first
Keywords :
digital arithmetic; integrated logic circuits; logic design; multiplying circuits; add/shift serial multiplier; digital FIR filters; most-significant-bit-first multiplier; serial multiplier; two´s complement type;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19950824
