• DocumentCode
    807930
  • Title

    Design of most-significant-bit-first serial multiplier

  • Author

    Lu, Shih-Lien ; Kenney, J.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
  • Volume
    31
  • Issue
    14
  • fYear
    1995
  • fDate
    7/6/1995 12:00:00 AM
  • Firstpage
    1133
  • Lastpage
    1135
  • Abstract
    The design of a two´s complement most-significant-bit-first add and shift serial multiplier is presented. In this multiplier, one of the multiplicands is represented in full length, whereas the second multiplicand is presented in a bit-serial fashion with the most significant bit (MSB) first
  • Keywords
    digital arithmetic; integrated logic circuits; logic design; multiplying circuits; add/shift serial multiplier; digital FIR filters; most-significant-bit-first multiplier; serial multiplier; two´s complement type;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19950824
  • Filename
    398577
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=807930