NMOS IC´s for clock and data regeneration in gigabit-per-second optical-fiber receivers

Author

Enam, S. Khursheed ; Abidi, Asad A.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

27

Issue

12

fYear

1992

fDate

12/1/1992 12:00:00 AM

Firstpage

1763

Lastpage

1774

Abstract

The design and performance of two essential analog circuits in optical-fiber receivers is described. A time-interleaved decision circuit is capable of regenerating 35-mV nonreturn-to-zero (NRZ) data inputs to full logic levels at 1.1 Gb/s with 10^-11 bit error rate (BER), and a phase-locked loop (PLL) extracts the clock from a 2 ²³ long pseudorandom sequence at 1.5 Gb/s with 13-ps r.m.s. jitter. The two circuits have been implemented as 1-μm NMOS ICs, and in their core area dissipate 200 and 350 mW, respectively

Keywords

MOS integrated circuits; analogue processing circuits; digital communication systems; linear integrated circuits; optical receivers; 1 micron; 1.1 Gbit/s; 1.5 Gbit/s; 200 mW; 350 mW; BER; NMOS ICs; analog circuits; bit error rate; clock regeneration; data regeneration; gigabit-per-second optical-fiber receivers; phase-locked loop; time-interleaved decision circuit; Analog circuits; Bit error rate; Clocks; Data mining; Logic circuits; MOS devices; Optical design; Optical receivers; Optical signal processing; Phase locked loops;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.173103

Filename

173103