A video digital signal processor with a vector-pipeline architecture

Author

Aono, Kunitoshi ; Toyokura, Masaki ; Araki, Toshiyuki ; Ohtani, Akihiko ; Kodama, Hisashi ; Okamoto, Kiyoshi

Author_Institution

Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

Volume

27

Issue

12

fYear

1992

fDate

12/1/1992 12:00:00 AM

Firstpage

1886

Lastpage

1894

Abstract

A 2-GOPS, 60-MIPS DSP with a new vector-pipeline architecture (VDSP: vector digital signal processor) has been developed for video CODEC systems, using 0.8-μm CMOS technology. The VDSP is programmable and can be adapted to handle various standards for video coding, such as those of CCITT H.261, MPEG (Moving Picture Experts Group), and JPEG (Joint Photographic Experts Group). It also contains a discrete cosine transform (DCT) core as one of the special processing units used to enhance performance. The 12.38-mm×12.90-mm VDSP, which consists of approximately 930 K transistors, operates at a maximum clock rate of 60 MHz. The encoder and the decoder specified in CCITT H.261 (full-CIF mode at 15 frames/s or more, 64 kb/s) can be realized with only two VDSP chips and only one VDSP chip, respectively

Keywords

CMOS integrated circuits; codecs; digital signal processing chips; discrete cosine transforms; image coding; pipeline processing; video signals; 0.8 micron; 60 MIPS; CCITT H.261; CMOS technology; JPEG; MPEG; decoder; discrete cosine transform core; encoder; programmable VDSP; vector digital signal processor; vector-pipeline architecture; video CODEC systems; video coding; video digital signal processor; CMOS process; CMOS technology; Clocks; Decoding; Digital signal processing; Digital signal processors; Discrete cosine transforms; MPEG standards; Video codecs; Video coding;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.173119

Filename

173119