Design techniques for high-speed, high-resolution comparators

Author

Razavi, Behzad ; Wooley, Bruce A.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

27

Issue

12

fYear

1992

fDate

12/1/1992 12:00:00 AM

Firstpage

1916

Lastpage

1926

Abstract

Precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described. Following a review of conventional offset cancellation techniques, circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented. The BiCMOS comparator consists of a preamplifier followed by two regenerative stages and achieves an offset of 200 μV at a 10-MHz clock rate while dissipating 1.7 mW. In the CMOS comparator offset cancellation is used in both a single-stage preamplifier and a subsequent latch to achieve an offset of less than 300 μV at comparison rates as high as 10 MHz, with a power dissipation of 1.8 mW

Keywords

BiCMOS integrated circuits; CMOS integrated circuits; analogue-digital conversion; comparators (circuits); linear integrated circuits; 1 micron; 1.7 mW; 1.8 mW; 2 micron; 5 V; BiCMOS comparator; CMOS comparator; analog-to-digital converters; clock rate; high-resolution comparators; latch; offset; offset cancellation techniques; parallel conversion stages; power dissipation; preamplifier; regenerative stages; single-stage preamplifier; BiCMOS integrated circuits; CMOS technology; Capacitors; Circuit synthesis; Clocks; Latches; Power dissipation; Preamplifiers; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.173122

Filename

173122