Title :
Quasi-adiabatic ternary CMOS logic
Author :
Mateo, D. ; Rubio, A.
Author_Institution :
Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
fDate :
1/18/1996 12:00:00 AM
Abstract :
Adiabatic switching is one technique for designing low power ICs. To diminish its expensive silicon area requirements a quasi-adiabatic ternary logic is proposed. The performances of a half adder using this logic have been obtained, showing a 65% area saving with respect to adiabatic binary logic
Keywords :
CMOS logic circuits; adders; logic gates; ternary logic; adiabatic switching; area requirements; half adder; low power ICs; quasi-adiabatic logic; ternary CMOS logic;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19960082
