• DocumentCode
    808519
  • Title

    Quasi-adiabatic ternary CMOS logic

  • Author

    Mateo, D. ; Rubio, A.

  • Author_Institution
    Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
  • Volume
    32
  • Issue
    2
  • fYear
    1996
  • fDate
    1/18/1996 12:00:00 AM
  • Firstpage
    99
  • Lastpage
    101
  • Abstract
    Adiabatic switching is one technique for designing low power ICs. To diminish its expensive silicon area requirements a quasi-adiabatic ternary logic is proposed. The performances of a half adder using this logic have been obtained, showing a 65% area saving with respect to adiabatic binary logic
  • Keywords
    CMOS logic circuits; adders; logic gates; ternary logic; adiabatic switching; area requirements; half adder; low power ICs; quasi-adiabatic logic; ternary CMOS logic;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19960082
  • Filename
    490860
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=808519