DocumentCode
809415
Title
The impact of gate-oxide breakdown on SRAM stability
Author
Rodriguez, Roberto ; Stathis, J.H. ; Linder, B.P. ; Kowalczyk, S. ; Chuang, C.T. ; Joshi, R.V. ; Northrop, G. ; Bernstein, K. ; Bhavnagarwala, A.J. ; Lombardo, S.
Author_Institution
Dept. d´Enginyeria Electronica, Univ. Autonoma de Barcelona, Spain
Volume
23
Issue
9
fYear
2002
Firstpage
559
Lastpage
561
Abstract
We have investigated the effects of oxide soft breakdown (SBD) on the stability of CMOS 6T SRAM cells. Gate-to-diffusion leakage currents of 20-50 μA at the n-FET source can result in a 50% reduction of noise margin. Breakdown at other locations in the cell may be less deleterious depending on n-FET width. This approach gives targets for tolerable values of leakage caused by gate-oxide breakdown.
Keywords
CMOS memory circuits; SRAM chips; dielectric thin films; integrated circuit reliability; leakage currents; semiconductor device breakdown; stability; 20 to 50 muA; CMOS 6T SRAM cells; SRAM stability; dielectric breakdown; gate-oxide breakdown; gate-to-diffusion leakage currents; n-FET width; noise margin; oxide reliability; oxide soft breakdown; static RAM; CMOS technology; Capacitors; Circuits; Electric breakdown; Failure analysis; Leakage current; MOS devices; Noise reduction; Random access memory; Stability;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2002.802600
Filename
1028999
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