A Low-Jitter Polyphase-Filter-Based Frequency Multiplier With Phase Error Calibration

Author

Yin, J.K. ; Chan, P.K.

Author_Institution

Inst. for Infocomm Res., Singapore

Volume

55

Issue

7

fYear

2008

fDate

7/1/2008 12:00:00 AM

Firstpage

663

Lastpage

667

Abstract

A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static phase error of the calibration circuit is 2.4 ps. The calibration leads to the normalized rms jitter of 0.049%.

Keywords

CMOS logic circuits; calibration; delay lock loops; digital filters; frequency multipliers; jitter; phase locked loops; CMOS process; frequency 200 MHz; frequency 25 MHz; low-jitter polyphase-filter-based frequency multiplier; phase error calibration circuit; size 0.13 mum; Bandwidth; Calibration; Circuits; Clocks; Delay; Filters; Frequency; Jitter; Oscillators; Phase locked loops; Calibration; delay-locked loop (DLL); frequency multiplier; phase-locked loop (PLL); polyphase filter (PPF);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2008.921571

Filename

4567632