From C to netlists: hardware engineering for software engineers?

The software programmable multiprocessor architecture has been employed extensively over the past two decades for embedded signal-processing applications. However, the increased complexity of such systems has, in many cases, required the use of hardware acceleration to meet the growing time-critical aspects of the design. Today´s field-programmable gate arrays (FPGAs) offer an alternative or additional acceleration platform, especially to an application-specific integrated circuit (ASIC). However, the traditional low-level development methods, such as schematic capture or hardware description languages (HDLs), employed to implement these hardware accelerated parts of the design result in a design lifecycle mismatch between the rapid development techniques available for the software programmable parts. This paper presents high-level design languages that enable users to generate netlists for FPGAs directly from high-level C-like languages, thereby offering an equivalent programming solution to that available with microprocessors. It details how one of these languages can be integrated into a high-level design flow for the rapid development of heterogeneous embedded signal-processing systems and presents results from a benchmark