Verifying SRAM designs

Author

Jenkins, Keifh A. ; Doyle, Scott E.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

8

Issue

5

fYear

1992

Firstpage

30

Lastpage

35

Abstract

Verifying the design and simulation of 256 K SRAM relies on measurements of waveforms on internal nodes along a critical path. A technique for producing accurate measurements of these waveforms using electron-beam probing is described. Comparisons of measured and simulated waveforms at several points on a chip are presented. It is shown that the measured signals agree with the simulation in regard to risetime, amplitude, and time delay along the path, thereby verifying the correctness of the device and circuit models used in the simulation. Slight deviations from the predicted time delay are the result of circuit design and process variations.<>

Keywords

SRAM chips; electron beam applications; integrated circuit testing; 256 kbit; SRAM designs; amplitude; circuit models; design verification; device models; electron-beam probing; risetime; simulation; static RAM; time delay; CMOS technology; Capacitance; Circuit simulation; Circuit testing; Electron beams; Random access memory; Semiconductor device measurement; Semiconductor device modeling; Signal design; Timing;

fLanguage

English

Journal_Title

Circuits and Devices Magazine, IEEE

Publisher

ieee

ISSN

8755-3996

Type

jour

DOI

10.1109/101.158510

Filename

158510