DocumentCode :
810845
Title :
A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting
Author :
Kotteri, K.A. ; Barua, S. ; Bell, A.E. ; Carletta, J.E.
Author_Institution :
Electr. & Comput. Eng. Dept., Virginia Tech, Blacksburg, VA, USA
Volume :
52
Issue :
5
fYear :
2005
fDate :
5/1/2005 12:00:00 AM
Firstpage :
256
Lastpage :
260
Abstract :
The filter bank approach for computing the discrete wavelet transform (DWT), which we call the convolution method, can employ either a nonpolyphase or polyphase structure. This work compares filter banks with an alternative polyphase structure for calculating the DWT-the lifting method. We look at the traditional lifting structure and a recently proposed "flipping" structure for implementing lifting. All filter bank structures are implemented on an Altera field-programmable gate array. The quantization of the coefficients (for implementation in fixed-point hardware) plays a crucial role in the performance of all structures, affecting both image compression quality and hardware metrics. We design several quantization methods and compare the best design for each approach: the nonpolyphase filter bank, the polyphase filter bank, the lifting and flipping structures. The results indicate that for the same image compression performance, the flipping structure gives the smallest and fastest, low-power hardware.
Keywords :
channel bank filters; convolution; data compression; discrete wavelet transforms; field programmable gate arrays; Altera field-programmable gate array; biorthogonal 9-7 DWT; convolution method; discrete wavelet transform; flipping structure; image compression quality; lifting method; low-power hardware; nonpolyphase filter bank; polyphase filter bank; polyphase structure; quantization method; Convolution; Design methodology; Discrete wavelet transforms; Field programmable gate arrays; Filter bank; Filtering; Finite impulse response filter; Hardware; Image coding; Quantization; Discrete wavelet transform (DWT); field-programmable gate array (FPGA); flipping; lifting; quantization;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2005.843496
Filename :
1431103
Link To Document :
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