Title :
IIR switched-capacitor decimator building blocks with optimum implementation
Author :
Franca, José A E ; Martins, Rui P.
Author_Institution :
Dept. de Engenharia Electrotecnica de Computadores, Inst. Superior Tecnico, Lisboa, Portugal
fDate :
1/1/1990 12:00:00 AM
Abstract :
The authors discuss the design of SC (switched-capacitor) decimators whose transfer functions have infinite impulse response (IIR). Novel optimum architectures are developed for which the speed requirements of the amplifiers are determined by the lower sampling rate, thus rendering the circuits particularly attractive for high-frequency applications. Appropriate Z-transfer functions are derived for first- and second-order IIR SC decimator building blocks. Design examples of optimum IIR SC decimators with different types of frequency response, as well as different factors of sampling rate reduction, are presented to demonstrate their practical feasibility
Keywords :
active networks; frequency response; switched capacitor networks; transfer functions; IIR switched-capacitor decimator; SC building blocks; Z-transfer functions; active circuits; amplifiers; first order type; frequency response; high-frequency applications; infinite impulse response; optimum architectures; optimum implementation; sampling rate reduction; second order type; speed requirements; Bandwidth; Circuits; Filtering; Finite impulse response filter; Frequency response; IIR filters; Sampling methods; Signal processing; Signal sampling; Transfer functions;
Journal_Title :
Circuits and Systems, IEEE Transactions on
