Dual-Bit/Cell SONOS Flash EEPROMs: Impact of Channel Engineering on Programming Speed and Bit Coupling Effect

Author

Datta, A. ; Kumar, P. Bharath ; Mahapatra, S.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., Mumbai

Volume

28

Issue

5

fYear

2007

fDate

5/1/2007 12:00:00 AM

Firstpage

446

Lastpage

448

Abstract

Programming performance of dual-bit silicon-oxide-nitride-oxide-silicon memories is studied on cells fabricated using different channel engineering schemes. Both halo and compensation implants are shown to impact the programming speed, bit coupling, and read disturb, and can be suitably adjusted to optimize the cell operation. The doping dependence of bit coupling and the programming speed are verified using well-calibrated 2-D device simulations

Keywords

flash memories; ion implantation; 2D device simulations; bit coupling effect; channel engineering; compensation implants; dual-bit SONOS Flash EEPROM; halo implants; localized charge storage; nonvolatile semiconductor memory; programming performance; programming speed; read disturb; Charge carrier processes; EPROM; Electrons; Flash memory; Implants; Nonvolatile memory; SONOS devices; Semiconductor device doping; Semiconductor memory; Silicon on insulator technology; 2-bit operation; Bit coupling; SONOS; compensation implant; flash; halo implant; localized charge storage; non volatile semiconductor memory (NVSM); program speed; read disturb;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2007.895406

Filename

4160016