• DocumentCode
    811018
  • Title

    March Test Generation Revealed

  • Author

    Benso, Alfredo ; Bosio, Alberto ; Carlo, Stefano Di ; Natale, Giorgio Di ; Prinetto, Paolo

  • Author_Institution
    Dept. of Control & Comput. Eng., Politec. di Torino, Turin
  • Volume
    57
  • Issue
    12
  • fYear
    2008
  • Firstpage
    1704
  • Lastpage
    1713
  • Abstract
    Memory testing commonly faces two issues: the characterization of detailed and realistic fault models and the definition of time-efficient test algorithms. Among the different types of algorithms proposed for testing static random access memories, march tests have proven to be faster, simpler, and regularly structured. The majority of the published march tests have been manually generated. Unfortunately, the continuous evolution of the memory technology introduces new classes of faults such as dynamic and linked faults and makes the task of handwriting test algorithms harder and not always leading to optimal results. Although some researchers published handmade march tests able to deal with new fault models, the problem of a comprehensive methodology to automatically generate march tests addressing both classic and new fault models is still an open issue. This paper proposes a new polynomial algorithm to automatically generate march tests. The formal model adopted to represent memory faults allows the definition of a general methodology to deal with static, dynamic, and linked faults. Experimental results show that the new automatically generated march tests reduce the test complexity and, therefore, the test time, compared to the well-known state of the art in memory testing.
  • Keywords
    automatic testing; computational complexity; random-access storage; continuous evolution; fault models; handwriting test algorithms; march test generation; memory testing; polynomial algorithm; static random access memories; test complexity; Algorithm design and analysis; Automatic testing; Fault detection; Fault diagnosis; Polynomials; Production; SRAM chips; Technical Activities Guide -TAG; Reliability; Test generation; Testing; and Fault-Tolerance;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2008.105
  • Filename
    4569834