Planar linear arrangements of outerplanar graphs

Author

Frederickson, Greg N. ; Hambrusch, Susanne E.

Author_Institution

Dept. of Comput. Sci., Purdue Univ., West Lafayette, IN, USA

Volume

35

Issue

3

fYear

1988

fDate

3/1/1988 12:00:00 AM

Firstpage

323

Lastpage

333

Abstract

Given an n-vertex outerplanar graph G, the problem is considered of arranging the vertices of G on a line so that no two edges cross and various cost measures are minimized. Efficient algorithms are presented for generating layouts in which every edge (i, j) and of G does not exceed a given bandwidth b(i, j), and the total edge length and the cutwidth of the layout are minimized. Characterizations of optimal layouts used by the algorithms are given. The algorithms combine sublayouts by solving two processor-scheduling problems. Although these scheduling problems are generally NP-complete, the instances generated by the algorithms are polynomial in n

Keywords

VLSI; graph theory; minimisation; network topology; scheduling; NP-complete; VLSI; cutwidth minimisation; layout generation; optimal layouts; outerplanar graphs; planar linear arrangements; total edge length minimisation; two processor-scheduling problems; Algorithm design and analysis; Area measurement; Bandwidth; Costs; Helium; Polynomials; Processor scheduling; Scheduling algorithm; Tree graphs; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0098-4094

Type

jour

DOI

10.1109/31.1745

Filename

1745