Title :
Planar embedding: linear-time algorithms for vertex placement and edge orderings
Author :
Jayakumar, R. ; Thulasiraman, K. ; Swamy, M.N.
Author_Institution :
Fac. of Eng. & Comput. Sci., Concordia Univ., Montreal, Que., Canada
fDate :
3/1/1988 12:00:00 AM
Abstract :
The problem of obtaining a planar embedding of a biconnected planar graph is discussed. The approach is based on the planarity testing algorithm of A. Lemple, et al. (1966) and its implementation using PQ-trees. In the planar embedding the vertices of the planar graph are placed in the plane at different horizontal and vertical levels so that no two distinct vertices appear in the same horizontal or vertical level, and higher-numbered vertices appear at higher vertical levels. The left-to-right order of the vertices in such a planar embedding is called the vertex order. For each vertex i, the anticlockwise order in which edges enter i from lower numbered neighbors is denoted by τ(i). Linear-time algorithms to determine a τ(i) for each i, and the vertex order, are developed. The vertex order captures the structural information about the relative placement of vertices in a planar embedding provided by the PQ-tree reduction algorithm. A systematic procedure to obtain an intersection-free drawing of the edges is described. A linear-time algorithm to construct a very compact horvert representation of a planar graph is also presented. This algorithm does not require the construction of the dual of the original graph
Keywords :
graph theory; network topology; PQ-tree reduction algorithm; biconnected planar graph; circuit layout; compact horvert representation; edge orderings; intersection-free drawing; linear-time algorithms; planar embedding; planarity testing algorithm; vertex placement; Circuit testing; Embedded computing; Gold; Integrated circuit layout; Integrated circuit testing; Printed circuits; Routing;
Journal_Title :
Circuits and Systems, IEEE Transactions on