DocumentCode :
811252
Title :
Vertical Flash Memory Cell With Nanocrystal Floating Gate for Ultradense Integration and Good Retention
Author :
Sarkar, Joy ; Dey, Sagnik ; Shahrjerdi, Davood ; Banerjee, Sanjay K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX
Volume :
28
Issue :
5
fYear :
2007
fDate :
5/1/2007 12:00:00 AM
Firstpage :
449
Lastpage :
451
Abstract :
We demonstrate a new vertical (3-D) Flash memory transistor cell with nanocrystals as the floating gate on the sidewalls that can form a high-retention ultrahigh density memory array. This scalable vertical cell architecture can allow a theoretical maximum array density of 1/(4F 2), where F is the minimum lithographic pitch, thus circumventing the integration density limitations of conventional planar Flash memory arrays. Discrete SiGe nanocrystals that are grown by conformal chemical vapor deposition process on the pillar sidewalls form the floating gate and render excellent retention properties at room temperature and at 85 degC. The cell shows a large memory window of ~1 V and endurance of more than 105 cycles
Keywords :
CVD coatings; Ge-Si alloys; flash memories; memory architecture; 1 V; 85 C; SiGe; conformal chemical vapor deposition; discrete nanocrystals; excellent retention properties; high-retention ultrahigh density memory array; nanocrystal floating gate; scalable vertical cell architecture; vertical flash memory cell; CMOS process; Chemical vapor deposition; Dielectrics; Flash memory; Flash memory cells; Germanium silicon alloys; Nanocrystals; Nonvolatile memory; Silicon germanium; Voltage; Flash; memory; nanocrystal; pillar; retention; sidewall; vertical;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2007.895445
Filename :
4160043
Link To Document :
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