DocumentCode :
811474
Title :
Design guideline for minimum channel length in silicon-on-insulator (SOI) MOSFET
Author :
Kawamoto, Akihiro ; Mitsuda, Hisatomo ; Omura, Yasuhisa
Author_Institution :
High-Technol. Res. Center/ORDIST & Graduate Sch. of Electron., Kansai Univ., Osaka, Japan
Volume :
50
Issue :
11
fYear :
2003
Firstpage :
2303
Lastpage :
2305
Abstract :
This brief proposes a preliminary design guideline for the minimum channel length in silicon-on-insulator (SOI) MOSFETs that is based on simulations of device characteristics. The simulations examine a wide variation in many device parameters to comprehensively evaluate device characteristics. A characteristic parameter that can successfully describe the minimum channel length is found. It is suggested that a sub-20-nm-channel single-gate SOI MOSFET with suppressed short-channel effects can be stably realized by optimizing its device parameters.
Keywords :
MOSFET; semiconductor device models; silicon-on-insulator; 5 to 20 nm; SOI MOSFETs; characteristic parameter; design guideline; device characteristics simulations; hydrodynamic transport model; minimum channel length; sub-20-nm-channel single-gate SOI MOSFET; suppressed short-channel effects; threshold voltage dependence; Dielectric devices; Doping profiles; Electrodes; FinFETs; Guidelines; Impurities; MOSFET circuits; Silicon on insulator technology; Substrates; Threshold voltage;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2003.819055
Filename :
1239077
Link To Document :
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