• DocumentCode
    811652
  • Title

    Memory-fast interfaces for DRAMs

  • Author

    Foss, R.C. ; Prince, B. ; Rodgers, R. ; Gustavson, David ; James, D.V. ; Stone, G. ; Kempainen, S.

  • Author_Institution
    Mosaid Technologies Inc., Kanata, Ont., Canada
  • Volume
    29
  • Issue
    10
  • fYear
    1992
  • Firstpage
    54
  • Lastpage
    57
  • Abstract
    The limitations of current nominal 5 V interfaces are examined, and the requirements for interfaces between high-speed DRAMs and processors are outlined. Three solutions are described. One is a center-tap-terminated interface, the second uses Gunning transceiver logic, and the third relies on low-voltage differential signaling.<>
  • Keywords
    DRAM chips; computer interfaces; 5 V; DRAMs; Gunning transceiver logic; LV; centre tap terminations; differential signaling; interfaces; processors; BiCMOS integrated circuits; Bipolar transistors; CMOS technology; Circuit testing; Costs; Logic circuits; Logic devices; Pins; Rail to rail outputs; Random access memory;
  • fLanguage
    English
  • Journal_Title
    Spectrum, IEEE
  • Publisher
    ieee
  • ISSN
    0018-9235
  • Type

    jour

  • DOI
    10.1109/6.158639
  • Filename
    158639
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=811652