VHDL: toward a unified view of design

A high-level view of the relevance of and relationships between key events in the development of the very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) is presented. Three phases in the life cycle of the language, the definition, development, and deployment phases, are outlined. The concept of a design information space, a convenient abstraction for categorizing various VHDL efforts and understanding their interrelationships, is introduced. Two representative VHDL examples dealing with performance modeling and testing are discussed. The waveform and vector exchange specification (WAVES) VHDL subset for the exchange of waveform descriptions is described.<>