DocumentCode
811699
Title
DSS: a distributed high-level synthesis system
Author
Roy, Jayanta ; Kumar, Nand ; Dutta, Rajiv ; Vemuri, Ranga
Author_Institution
Cincinnati Univ., OH, USA
Volume
9
Issue
2
fYear
1992
fDate
6/1/1992 12:00:00 AM
Firstpage
18
Lastpage
32
Abstract
DSS, a large-scale ongoing exercise in developing parallel algorithms for high-level synthesis and implementing them in an integrated distributed system to evaluate their individual and collective effectiveness, is discussed. Embedded in a very-high-speed integrated circuit hardware description language (VHDL) centered design environment, DSS consists of a collection of parallel algorithms executing on a multiple input, multiple data (MIMD) multiprocessor machine. The system uses coarse-grained parallelism to explore and evaluate many alternative VLSI designs efficiently. DSSs internal organization and its scheduling, register optimization, interconnection formation, and controller generation techniques are described. Results illustrating DSS performance with respect to design quality, and the efficiency of the DSS algorithms in a multiprocessor environment are presented.<>
Keywords
VLSI; circuit analysis computing; distributed processing; parallel algorithms; scheduling; specification languages; MIMD; VHDL; VLSI designs; coarse-grained parallelism; controller generation; design quality; distributed high-level synthesis system; integrated distributed system; interconnection formation; multiprocessor machine; parallel algorithms; performance; register optimization; scheduling; very-high-speed integrated circuit hardware description language; Algorithm design and analysis; Decision support systems; Hardware design languages; High level synthesis; Large scale integration; Parallel algorithms; Scheduling; Spread spectrum communication; Very high speed integrated circuits; Very large scale integration;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.143143
Filename
143143
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