A VHDL fault diagnosis tool using functional fault models

The development and implementation of an algorithm that forms the basis of a very-high-speed integrated circuit hardware description language (VHDL) fault diagnosis tool (VFDT) are discussed. Given a VHDL description, a compiler creates an internal representation suitable for simulation and fault diagnosis. VFDT diagnoses faults in this representation hierarchically using the stuck-at fault model at the first level and the arbitrary-failure model at the second level. It reasons from first principles by means of constraint suspension. Examples of fault diagnosis using the VFDT are described.<>