A GaAs MESFET with a partially depleted p layer for SRAM applications

Author

Noda, Minoru ; Hosogi, Kenji ; Sumitani, Kouichi ; Nakano, Hirofumi ; Nishitani, Kazuo ; Otsubo, Mutsuyuki ; Makino, Hiroshi ; Tada, Akiharu

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

Volume

38

Issue

12

fYear

1991

fDate

12/1/1991 12:00:00 AM

Firstpage

2590

Lastpage

2598

Abstract

A GaAs MESFET with a partially depleted p layer that has a specific application to SRAMs has been developed. The short-channel effect is well suppressed for gate lengths down to 0.5 μm by a rather dense p layer buried under the channel. Its acceptor ion dose is as high as 2×10¹² cm^-2, which corresponds to a partially depleted condition. As for applications for SRAMs, it is possible to attain fully functional 7-ns 4-kb SRAMs that are operative at 75°C by using the FET with a 1-μm gate. A chip yield of 22% has been achieved in a 3-in wafer

Keywords

III-V semiconductors; SRAM chips; Schottky gate field effect transistors; field effect integrated circuits; gallium arsenide; 0.5 micron; 1 micron; 4 kbit; 7 ns; 75 degC; GaAs; MESFET; SRAM applications; acceptor ion dose; chip yield; gate lengths; partially depleted p-layer; short-channel effect; FETs; Gallium arsenide; HEMTs; Heterojunction bipolar transistors; Large scale integration; MESFETs; Microscopy; Parasitic capacitance; Random access memory; Scattering;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.158680

Filename

158680