DocumentCode :
811919
Title :
Best structures for deep submicrometer (0.1-0.3 μm) MOS devices
Author :
Tasch, A.F.
Author_Institution :
Texas Univ., Austin, TX
Volume :
38
Issue :
12
fYear :
1991
fDate :
12/1/1991 12:00:00 AM
Firstpage :
2688
Abstract :
Summary form only given. The LDD-type structure has begun to encounter difficulties in satisfying transistor requirements in manufacturing due to a basic conflict between the need to have a graded drain profile for hot carrier suppression and the requirements for manufacturability and performance which place emphasis on a shallow, steeply profiled drain. One approach for overcoming this conflict and limitation is a MOS transistor structure called the hot-carrier suppressed (HCS) MOSFET. In this approach, a lower doped drain region is placed behind, or above, the shallow, heavier doped drain region rather than being placed adjacent to the channel region. This structure is described in detail, and its simulated performance compared with that of the LDD and conventional MOSFET structures
Keywords :
doping profiles; hot carriers; insulated gate field effect transistors; semiconductor technology; 0.1 to 0.3 micron; LDD-type structure; MOS transistor structure; deep submicrometre MOSFET; graded drain profile; hot carrier suppressed MOSFET; hot carrier suppression; lower doped drain region; manufacturability; shallow steeply profiled drain; simulated performance; Conducting materials; Integrated circuit technology; MOS devices; MOSFET circuits; Manufacturing; Optical polymers; Organic light emitting diodes; Power supplies; Transistors; Voltage;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.158694
Filename :
158694
Link To Document :
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