• DocumentCode
    81224
  • Title

    Low-Power Test Generation by Merging of Functional Broadside Test Cubes

  • Author

    Pomeranz, Irith

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • Volume
    22
  • Issue
    7
  • fYear
    2014
  • fDate
    Jul-14
  • Firstpage
    1570
  • Lastpage
    1582
  • Abstract
    This paper describes a low-power test generation procedure, which targets the switching activity during the fast functional clock cycles of broadside tests. The procedure is based on merging of test cubes that it extracts from functional broadside tests. The use of test cube merging supports test compaction and it can be used for accommodating the constraints of test data compression. The use of functional broadside tests provides a target for the switching activity of low-power tests, which does not exceed the switching activity that is possible during functional operation, or that the circuit is designed for. The use of test cubes that are extracted from functional broadside tests is a unique feature of this procedure. It ensures that the low-power tests would create functional operation conditions in subcircuits that are defined by the test cubes. Experimental results show that the procedure detects all or almost all the transition faults that are detectable by arbitrary (functional and nonfunctional) broadside tests in benchmark circuits.
  • Keywords
    circuit testing; data compression; fault tolerance; low-power electronics; switching circuits; arbitrary broadside tests; benchmark circuits; fast functional clock cycles; functional broadside tests; low-power test generation procedure; subcircuits; switching activity; test compaction; test cubes merging; test data compression; transition faults; Circuit faults; Clocks; Compaction; Merging; Switches; Switching circuits; Test data compression; Functional broadside tests; low-power test generation; test cubes; transition faults; transition faults.;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2013.2275037
  • Filename
    6578179