DocumentCode
812243
Title
Isolation charge pump fabricated in silicon on sapphire CMOS technology
Author
Culurciello, E. ; Pouliquen, P.O. ; Andreou, A.G.
Author_Institution
Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
Volume
41
Issue
10
fYear
2005
fDate
5/12/2005 12:00:00 AM
Firstpage
590
Lastpage
592
Abstract
The design, fabrication and testing of a four-stage charge-pump fabricated in a 0.5 μm silicon-on-sapphire CMOS technology is reported. The charge pump can generate a 2.68 V output with a 3.3 V input power supply, consuming 2.5 mA. The performance of the architecture is optimised by judiciously employing MOS transistors with different threshold (0, 0.3 and 0.7 V) in the different parts of the circuit. The charge pump input and output power supplies are galvanically isolated to over 800 V by means of the dielectric properties of the coupling capacitors and the insulating sapphire substrate.
Keywords
CMOS integrated circuits; MOSFET; power supply circuits; sapphire; silicon-on-insulator; 0.5 micron; 2.5 mA; 2.68 V; 3.3 V; MOS transistors; coupling capacitors; dielectric properties; isolation charge pump; sapphire substrate; silicon on sapphire CMOS technology;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20050312
Filename
1432535
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