DocumentCode
812656
Title
Integration of poly buffered LOCOS and gate processing for submicrometer isolation technique
Author
Hillenius ; Chen, M.L.
Volume
38
Issue
12
fYear
1991
fDate
12/1/1991 12:00:00 AM
Firstpage
2721
Abstract
Summary form only given. A modified poly buffered LOCOS (PBL) process is described which simplifies processing and provides advantages over conventional PBL and LOCOS processes. The use of a poly buffer between the pad oxide and the nitride layer offers the opportunity of integrating the poly gate deposition and the field isolating process and overcomes the processing difficulties of the conventional PBL while maintaining the advantage of a narrow spacing between active areas (THINOX). The process sequence of the conventional PBL and the integrated PBL (IPBL) process are summarized
Keywords
integrated circuit technology; THINOX; field isolating process; gate processing; nitride layer; pad oxide; poly buffered LOCOS; submicrometer isolation technique; submicron IC process; Buffer layers; Current density; Etching; Gallium arsenide; Heterojunction bipolar transistors; III-V semiconductor materials; Leakage current; Springs; Stress; Zinc compounds;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.158759
Filename
158759
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