Title :
Characterization of back-channel subthreshold conduction of walled SOI devices
Author :
Chen, Huanting ; Yue, Jing ; Dougal, G.
Author_Institution :
Honeywell SSEC, Plymouth, MN
fDate :
12/1/1991 12:00:00 AM
Abstract :
Summary form only given. Submicrometer CMOS transistors with junctions walled to a trenched isolation oxide have been fabricated on SIMOX substrates. Back-channel leakage of the devices was measured as a function of substrate bias. Compared with nonwalled devices, walled devices showed early turn-on of the back-channel at relatively low substrate biases. This phenomenon is caused by the two-dimensional electrical field effect at the bottom corner of the device sidewalls, and is supported by PISCES simulation
Keywords :
CMOS integrated circuits; electric field effects; leakage currents; semiconductor-insulator boundaries; CMOS transistors; PISCES simulation; SIMOX substrates; Si; back channel leakage; back-channel subthreshold conduction; submicron transistors; substrate bias; trenched isolation oxide; two-dimensional electrical field effect; walled SOI devices; Degradation; Drain avalanche hot carrier injection; Electrons; Hot carriers; MOS devices; MOSFET circuits; Microstructure; Subthreshold current; Very large scale integration; Virtual colonoscopy;
Journal_Title :
Electron Devices, IEEE Transactions on
