Analysis of a hybrid analog/switched-capacitor phase-locked loop

A detailed analysis is presented of the HPLL (hybrid phase-locked loop). Nonlinear state descriptions of the first- and second-order HPLLs are obtained. These descriptions are suitable for deterministic analyses. The locations of steady-state equilibrium operating points are given, along with relevant stability conditions. Also, a small signal model for loops of arbitrary order is presented. The behavior of the HPLL for random inputs is also treated, where the input consists of a sinusoid plus random Gaussian noise. Both linear and nonlinear analyses are presented. The results of the analyses performed are substantiated by both computer simulation and laboratory measurements on a discrete prototype. The analyses are directly applicable to standard SC (switched-capacitor) PLLs, for which no comprehensive analysis have previously been performed. Thus, the results presented are useful for systems designers using SC PLLs as well as for those using the HPLL