Short-channel pMOSTs in a high-resistivity silicon substrate. I. Analytical model

The behavior of short-channel pMOS transistors (2.5-25 μm) in a high-resistivity silicon substrate (3-10 kΩ-cm), resulting from a 3-μm CMOS process, especially optimized for the integration of totally depleted p-i-n type detectors and their readout electronics, is described both qualitatively and quantitatively. Their behavior is examined both in the off-region, where bulk punchthrough and space-charge limitations prevail, and in the on-region. Simulations and experimental data show that these transistors exhibit a second linear region, referred to as quasi-linear region, instead of the normal saturation region