Short-channel pMOSTs in a high-resistivity silicon substrate. I. Analytical model

Author

Vanstraelen, Guy ; Simoen, Eddy ; Claeys, Cor ; Declerck, Gilbert J.

Author_Institution

IMEC, Leuven, Belgium

Volume

39

Issue

10

fYear

1992

fDate

10/1/1992 12:00:00 AM

Firstpage

2268

Lastpage

2277

Abstract

The behavior of short-channel pMOS transistors (2.5-25 μm) in a high-resistivity silicon substrate (3-10 kΩ-cm), resulting from a 3-μm CMOS process, especially optimized for the integration of totally depleted p-i-n type detectors and their readout electronics, is described both qualitatively and quantitatively. Their behavior is examined both in the off-region, where bulk punchthrough and space-charge limitations prevail, and in the on-region. Simulations and experimental data show that these transistors exhibit a second linear region, referred to as quasi-linear region, instead of the normal saturation region

Keywords

insulated gate field effect transistors; semiconductor device models; space-charge-limited conduction; 2.5 to 25 micron; 3 micron; 3 to 10 kohmcm; CMOS process; Si; bulk punchthrough; high resistivity Si substrate; on-region; p-channel devices; p-i-n type detectors; pMOS transistors; pMOST; quasilinear region; readout electronics; short-channel; space-charge limitations; Analytical models; CMOS process; CMOS technology; Detectors; Doping; MOSFETs; PIN photodiodes; Silicon; Superconducting device noise; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.158798

Filename

158798