Examination of gradual-junction p-MOS structures for hot carrier control using a new lifetime extraction method

The effect of junction engineering on the hot carrier lifetimes of p-MOS transistors is examined. A normalizing method for predicting lifetimes is developed and used to show that a critical parameter controlling the lifetimes of submicrometer p-MOS devices is the size of the hot-carrier-damaged region. This is verified on conventional and gradual-junction transistors, where different implant species and energies were used to alter the source and drain junction profiles. Conventional junction devices with gate currents up to 100 times larger than those of gradual junction devices were found to have the same lifetimes as gradual junctions devices for the same effective transistor length. It is concluded that, contrary to n-MOS transistors, controlling the size of the damage region is as important as, if not more important than, reducing the hot electron gate currents by junction engineering in p-MOS devices