Title :
Fast locking delay-locked loop using initial delay measurement
Author :
Kim, Taesung ; Wang, Sung Ho ; Kim, Beomsup
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., YuseongGu, South Korea
fDate :
8/15/2002 12:00:00 AM
Abstract :
A delay-locked loop (DLL) architecture capable of incorporating fast locking and low jitter features simultaneously is reported. A test chip was fabricated in a 0.6 μm CMOS process to prove its functionality. The proposed DLL can align the internal clock to the external reference clock within two cycles and maintain its locking state with the aid of feedback operation
Keywords :
CMOS digital integrated circuits; circuit feedback; clocks; delay lock loops; timing jitter; 0.6 micron; CMOS process; delay-locked loop architecture; double-poly double-metal CMOS technology; external reference clock; fast locking delay-locked loop; feedback operation; initial delay measurement; internal clock alignment; locking state maintenance; low jitter; register controlled DLL; synchronous mirror DLL; test chip;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20020626
