DocumentCode
813249
Title
5 V, 8 bit, 100 MS/s fully differential CMOS sample-and-hold amplifier
Author
Chen, Chun-Chieh ; Tsao, Hen-Wai
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
32
Issue
4
fYear
1996
fDate
2/15/1996 12:00:00 AM
Firstpage
287
Lastpage
288
Abstract
A 5 V, 100 MS/s fully differential CMOS sample-and-hold amplifier (SHA) with 8 bit accuracy is proposed. Based on the stability limitations of closed-loop SHAs studied in a previous paper (see Int. J. Electron., vol. 78, no. 5, p. 907-910, 1995), the proposed SHA is implemented by an open-loop structure using the `gain-enhanced unity-gain amplifier´ to avoid the stability problem and achieve higher operation speed. Simulation results which agree well with experimental results have been obtained to demonstrate the accuracy of the proposed circuit
Keywords
CMOS analogue integrated circuits; differential amplifiers; sample and hold circuits; 5 V; CMOS S/H amplifier; fully differential amplifier; gain-enhanced unity-gain amplifier; open-loop structure; sample/hold amplifier; stability limitations;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19960234
Filename
490922
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