Title :
Parallelised max-Log-Map model
Author :
Loo, K.K. ; Salman, K. ; Alukaidey, T. ; Jimaa, S.A.
Author_Institution :
Dept. of ECEE, Hertfordshire Univ., Hatfield, UK
fDate :
8/15/2002 12:00:00 AM
Abstract :
A parallelised max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-Log-MAP algorithm; and therefore facilitates easy implementation
Keywords :
computational complexity; decoding; parallel algorithms; signal processing; turbo codes; 3GPP turbo codes; DSP; VLIW architecture; computational complexity reduction; decoding; digital signal processor; max-Log-MAP algorithm; microprocessor; parallelised max-Log-MAP model; sub-word parallelism; very long instruction word architecture;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20020663
