Extremely scaled silicon nano-CMOS devices

Author

Chang, Leland ; Choi, Yang-kyu ; Ha, Daewon ; Ranade, Pushkar ; Xiong, Shiying ; Bokor, Jeffrey ; Hu, Chenming ; King, Tsu-Jae

Author_Institution

Electr. Eng. & Comput. Sci. Dept., Univ. of California, Berkeley, CA, USA

Volume

91

Issue

11

fYear

2003

fDate

11/1/2003 12:00:00 AM

Firstpage

1860

Lastpage

1873

Abstract

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.

Keywords

CMOS integrated circuits; MOSFET; carrier mobility; integrated circuit metallisation; molybdenum; nanoelectronics; nanolithography; semiconductor device metallisation; silicon-on-insulator; work function; 10 nm; 15 nm; FinFET; Mo; Si-SiO₂; carrier mobility; circuit performance; crystal orientation; double-gate device structure; extremely scaled silicon nano-CMOS devices; gate length scaling; gate workfunction engineering; high-performance planar ultrathin-body devices; nanometer regime; process-induced variation sensitivity; roughness; silicon-on-insulator substrates; sublithographic patterning; CMOS technology; Circuit optimization; Electrodes; FinFETs; MOSFET circuits; Nanoscale devices; Paper technology; Silicon on insulator technology; Substrates; Transistors;

fLanguage

English

Journal_Title

Proceedings of the IEEE

Publisher

ieee

ISSN

0018-9219

Type

jour

DOI

10.1109/JPROC.2003.818336

Filename

1240075