Title :
Minimisation technique for series-gated emitter-coupled logic
Author :
Choy, C.S. ; Jones, P.L.
Author_Institution :
Dept. of Electron., Chinese Univ. of Hong Kong, Shatin NT, Hong Kong
fDate :
6/1/1989 12:00:00 AM
Abstract :
The authors describe a systematic technique to synthesise series-gated emitter-coupled logic (ECL). The technique is applied in an autosynthesis program whereby multilevel ECL circuit schematics are generated automatically from Boolean equation or truth table input.<>
Keywords :
circuit CAD; emitter-coupled logic; integrated logic circuits; logic CAD; minimisation of switching nets; Boolean equation; CAD; automatic schematic generation; autosynthesis program; computer aided design; emitter-coupled logic; logic synthesis; minimisation technique; multilevel ECL circuit schematics; series gated ECL; truth table input; Design automation; Emitter coupled logic; Minimization methods;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings G
