Title :
Design of stuck-open fault testable CMOS complex gates
Author :
Tsiatouhas, Y. ; Haniotakis, Th ; Halatsis, C. ; Arapoyanni, A.
Author_Institution :
Dept. of Inf., Athens Univ., Greece
fDate :
2/15/1996 12:00:00 AM
Abstract :
Tests that detect transistor stuck-open (TSOP) faults independent of timing skews in input changes may not exist for all TSOP faults in CMOS complex gates. A new design method is presented which does not require any extra hardware or test inputs to improve the testability of a CMOS complex gate
Keywords :
CMOS logic circuits; design for testability; fault location; logic design; logic gates; logic testing; CMOS complex gates; design; testability; timing skews; transistor stuck-open faults;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19960247
