Transmission gate-interfaced APDL design

Based on the recent adiabatic pseudo domino logic (APDL), a new circuit structure, transmission gate-interfaced APDL (T-APDL), is proposed to improve the performance of the APDL circuit, especially for power consumption, operating voltage and frequency characteristics. Although an additional transistor is required in the basic T-APDL structure, the power saving compared to APDL is significant and the proposed circuits have been simulated to function in excess of 400 MHz and as low as 2 V. Both structures have been fully simulated using HSPICE, with 0.8 μm, n-well CMOS process parameters, and the results are presented here. The generation of the control signals for the transmission gate (T-gate) is also discussed